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dual, 1 2- bit, 80 msps/125 msps , serial lvds 1.8 v analog - to - digital converter data sheet ad9635 rev. b document feedback information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent ri ghts of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062 - 9106, u.s.a. tel: 781.329.4700 ? 2012C 2015 analog devices, inc. all rights reserved. technical support www.analog.com features 1.8 v supply operation low p ower: 115 mw per channel at 125 msps with scalable power options snr = 7 1 db fs (to nyquist) sfdr = 93 dbc at 70 mhz dnl = ? 0.1 lsb to +0.2 lsb (typical); inl = 0.4 lsb (typical) serial lvds (ansi - 644, def ault) and l ow power, reduced range option (similar to ieee 1596.3) 650 mhz full power analog bandwidth 2 v p - p input voltage range serial port control full chip and individual channel power - down modes flexible bit orientation built - in and custom digital test pattern generation c lock divider programmable output clock and data alignment programmable output resolution standby mode applications communications diversity radio systems multimode digital receivers gsm, edge, w - cdma, lte, cdma2000, wimax, td - scdma i/q demodulation systems smart antenna systems broadband data applications battery - powered instruments hand held scope meters portable medic al imaging and ultrasound r adar/lidar general description the ad963 5 is a dual , 1 2 - bit, 80 msps /125 msps analog - to - digital con verter (adc) with an on - chip sample - and - hold circuit designed for low cost, low power, small size, and ease of use. the product operates at a conversion rate of up to 125 msps and is optimized for outstanding dynamic performance and low power in applications wher e a small package size is critical. the adc requires a single 1.8 v power supply and lvpecl - / cmos - /lvds - compatible sample rate clock for full performance operation. no external reference or driver components are required for many applications. functional block diagram figure 1 . the adc automatically multiplies the sample rate clock for the appropriate lvds serial data rate. a data clock output (dco) for capturing data on the output and a frame clock output (fco) for signaling a new outpu t byte are provided. individual channel power - down is supported ; the ad963 5 typically consumes less than 2 mw in the full power - down state . th e adc provide s several features designed to maximize flexibility and minimize system cost, such as programmable output clock and data align - ment and digital test pattern generation. the available digital test patterns include built - in deterministic and pse udorandom patterns, along with custom user - defined test patterns entered via the serial port interface (spi). the ad963 5 is available in a rohs - compliant, 32- lead lfcsp. it is specified over the industrial temperature range o f ?40c to +85c. product highlights 1. small footprint. two adcs are contained in a small, space - saving package. 2. low p ower . the ad963 5 uses 11 5 mw /channel at 125 msps with scalable power options . 3. pin c ompatibility with the ad9645 , a 1 4 - b it d ual adc. 4. ease of use. a data clock output (dco) operates at frequencies of up to 500 mhz and supports double data rate (ddr) operation. 5. user flexibility. spi control offers a wide range of flexible features to meet specific system requirements. reference ad9635 12 vina+ avdd drvdd 12 12 vinb+ vinb? d0a+ 12 d0b+ vina? vcm d1a+ d1b+ agnd d0a? d1a? d0b? d1b? dco+ dco? fco+ fco? 12-bit pipeline adc 12-bit pipeline adc pll, serializer and ddr lvds drivers serial port interface 1 to 8 clock divider sclk/ dfs sdio/ pdwn csb clk+ clk? 10577-001
ad9635* product page quick links last content update: 02/23/2017 comparable parts view a parametric search of comparable parts. evaluation kits ? ad9635 evalution board documentation application notes ? an-1142: techniques for high speed adc pcb layout ? an-501: aperture uncertainty and adc system performance ? an-737: how adisimadc models an adc ? an-827: a resonant approach to interfacing amplifiers to switched-capacitor adcs ? an-835: understanding high speed adc testing and evaluation ? an-878: high speed adc spi control software ? an-905: visual analog converter evaluation tool version 1.0 user manual ? an-935: designing an adc transformer-coupled front end data sheet ? ad9635: dual, 12-bit, 80 msps/125 msps, serial lvds 1.8 v analog-to-digital converter user guides ? ad9655/ad9645/ad9635 evaluation documentation tools and simulations ? visual analog ? ad9635 ibis model ? ad9635 s-parameter reference materials press ? analog devices dual 14-bit a/d converter reduces power and size in communications, instrumentation, test and measurement applications technical articles ? ms-2210: designing power supplies for high speed adc design resources ? ad9635 material declaration ? pcn-pdn information ? quality and reliability ? symbols and footprints discussions view all ad9635 engineerzone discussions. sample and buy visit the product page to see pricing options. technical support submit a technical question or find your regional support number. document feedback submit feedback for this data sheet. this page is dynamically generated by analog devices, inc., and inserted into this data sheet. a dynamic change to the content on this page will not trigger a change to either the revision number or the content of the product data sheet. this dynamic page may be frequently modified.
ad9635 data sheet rev. b | page 2 of 36 table of contents features .............................................................................................. 1 applications ....................................................................................... 1 general descript ion ......................................................................... 1 functional block diagram .............................................................. 1 product highlights ........................................................................... 1 revision history ............................................................................... 2 specifications ..................................................................................... 3 dc specifications ......................................................................... 3 ac specifications .......................................................................... 4 digital specifications ................................................................... 5 switching specifications .............................................................. 6 timing specifications .................................................................. 6 absolute maximum ratings .......................................................... 10 thermal resistance .................................................................... 10 esd cautio n ................................................................................ 10 pin configuration and function descriptions ........................... 11 typical performance characteristics ........................................... 12 ad963 5 - 80 ................................................................................... 12 ad963 5 - 125 ................................................................................. 15 equivalent circuits ......................................................................... 18 theory o f operation ...................................................................... 19 analog input considerations .................................................... 19 voltage reference ....................................................................... 20 clock inpu t considerations ...................................................... 21 power dissipation and power - down mode ........................... 22 digital outputs and timing ..................................................... 23 output test modes ..................................................................... 26 serial por t interface (spi) .............................................................. 27 configuration using the spi ..................................................... 27 hardware interface ..................................................................... 28 configuration without the spi ................................................ 28 spi accessible features .............................................................. 28 memory map .................................................................................. 29 reading the memory map register table ............................... 29 memory map register table ..................................................... 30 me mory map register descriptions ........................................ 33 applications information .............................................................. 35 design guidelines ...................................................................... 35 power and ground guidelines ................................................. 35 clock stability considerations ................................................. 35 exposed pad thermal heat slug recommendations ............ 35 vcm ............................................................................................. 35 reference decoupling ................................................................ 35 spi port ........................................................................................ 35 outline dimensions ....................................................................... 36 ordering guide .......................................................................... 36 revisio n history 10/15 rev. a to rev. b changed t sample /16 to t sample /12 , ad9516 to ad9516 - 0/ ad9516 - 1 /ad9516 - 2/ad9516 - 3/ad9516 - 4/ad9516 - 5, and ad9517 to ad9517 - 0/ad9517 - 1/ad9517 - 2/ad9517 - 3/ ad9517 - 4 ....................................................................... throughout changes to general description section ...................................... 1 added endnote 4 , table 4 ............................................................... 6 changes to digital outputs and timing section ....................... 25 8 /14 rev. 0 to rev. a added propagation delay parameters of 1.5 ns (min) and 3.1 ns (max) , tabl e 4 ................................................................. 6 changes to figure 2 and figure 3 ................................................... 7 changes to figure 4 and figure 5 ................................................... 8 changes to pin 21 description ..................................................... 1 1 changes to voltage reference section ......................................... 2 0 changes to table 11 ....................................................................... 2 5 changes to first paragraph of serial port interface (spi) section .............................................................................................. 27 changes to spi accessible features section ............................... 2 8 changes to output phase (register 0x16) bits[6:4] input clock phase adjust section ........................................................... 3 3 changes to resolution/sample rate override (register 0x100) section and user i/o control 3 (register 0x102) bit 3 vcm po wer - down section ..................................................................... 3 4 added clock sta bility considerations section ........................... 3 5 6/12 revision 0: initial version
data sheet ad9635 rev. b | page 3 of 36 specifications dc s pecifications avdd = 1.8 v, drvdd = 1.8 v, 2 v p - p differential input, 1.0 v internal reference, ain = ?1.0 dbfs, unless otherwise noted. table 1. parameter 1 temp ad963 5 - 80 ad963 5 - 125 min typ max min typ max unit resolution 12 12 bits accuracy no missing codes full guaranteed guaranteed offset error full ? 0.6 ? 0.3 + 0.1 ? 0.6 ? 0.3 + 0.2 % fsr offset matching full ? 0.2 +0. 1 + 0.4 ? 0.2 +0. 1 + 0.4 % fsr gain error full ? 4.0 ? 0.8 + 2.1 ? 4.7 ? 0.4 + 4.8 % fsr gain matching full 0.5 2.4 0.6 2.9 % fsr differential nonlinearity (dnl) full ? 0.2 + 0.4 ? 0.3 + 0. 6 lsb 25c ? 0.1 to +0.2 ? 0.1 to +0.2 lsb integral nonlinearity (inl) full ? 0.7 + 0.7 ? 1.1 + 1.1 lsb 25c 0.3 0.4 lsb temperatu re drift offset error full 2.9 3.7 ppm/ c internal voltage reference output voltage (1 v mode) full 0.98 1.0 1.02 0.98 1.0 1.02 v load r egulation at 1.0 ma (v ref = 1 v) 25c 2 2 mv input resistance 25c 7.5 7.5 k input - referred noise v ref = 1.0 v 25c 0.41 0.42 lsb rms an alog inputs differential input voltage (v ref = 1 v) full 2 2 v p -p common - mode voltage full 0.9 0.9 v common - mode range 25c 0.5 1.3 0.5 1.3 v differential input resistance 25c 5.2 5.2 k differential input capacitance 25c 3.5 3.5 pf power supply avdd full 1.7 1.8 1.9 1.7 1.8 1.9 v drvdd full 1.7 1.8 1.9 1.7 1.8 1.9 v i avdd 2 full 57 61 75 81 ma i drvdd (ansi - 644 mode) 2 full 45 47 52 55 ma i drvdd (reduced range mode) 2 25c 36 43 ma total power consumption dc input full 174 186 215 232 mw sine wave input ( two channels ; includes output drivers in ansi - 644 mode) full 184 194 229 245 mw sine wave input ( two channels ; includes output drivers in reduced range mode) 25c 167 212 mw power - down 25c 2 2 mw standby 3 full 91 99 114 124 mw 1 see the an - 835 application note , understanding high speed adc testing and evaluation , for definitions and for details on how these tests were completed. 2 measured with a low input frequency, full - scale sine wave on both channels. 3 can be controlled via the spi.
ad9635 data sheet rev. b | page 4 of 36 ac specifications avdd = 1.8 v, drvdd = 1.8 v, 2 v p - p differential input, 1.0 v internal reference, ain = ? 1.0 dbfs, unless otherwise noted. table 2. parameter 1 temp ad963 5 - 80 ad963 5 - 125 unit min typ max min typ max signal - to - noise ratio (snr) f in = 9.7 mhz 25c 7 1.8 7 1.5 dbfs f in = 30.5 mhz 25c 7 1 .7 7 1.5 dbfs f in = 70 mhz full 70.6 71.2 70.1 71.1 dbfs f in = 1 39.5 mhz 25c 69.9 7 0.2 dbfs f in = 200 .5 mhz 25c 68.4 68.9 dbfs signal - to - noise - and - distortion ratio (sinad) f in = 9.7 mhz 25c 7 1.8 7 1.5 dbfs f in = 30. 5 mhz 25c 7 1 .6 7 1.5 dbfs f in = 70 mhz full 70.5 71.2 69.7 71.1 dbfs f in = 1 39.5 mhz 25c 69.6 7 0.2 dbfs f in = 200 .5 mhz 25c 68.2 68.7 dbfs effective number of bits (enob) f in = 9.7 mhz 25c 11.6 11.6 bits f in = 30.5 mhz 25c 11.6 11.6 bits f in = 70 mhz full 11.4 11.5 11.3 11.5 bits f in = 1 39.5 mhz 25c 11. 3 11. 4 bits f in = 200 .5 mhz 25c 11. 0 11. 1 bits spurious - free dynamic range (sfdr) f in = 9.7 mhz 25c 93 92 dbc f in = 30.5 mhz 25c 9 0 9 3 dbc f in = 70 mhz full 82 94 8 2 9 3 dbc f in = 1 39.5 mhz 25c 8 1 92 dbc f in = 200 .5 mhz 25c 8 2 83 dbc worst har monic (second or third) f in = 9.7 mhz 25c ? 9 3 ? 9 2 dbc f in = 30.5 mhz 25c ? 9 0 ? 9 3 dbc f in = 70 mhz full ? 94 ? 85 ? 9 3 ? 8 2 dbc f in = 1 39.5 mhz 25c ? 8 1 ? 9 2 dbc f in = 200 .5 mhz 25c ? 8 2 ? 83 dbc worst oth er harmonic or spur f in = 9.7 mhz 25c ? 96 ? 95 dbc f in = 30.5 mhz 25c ? 95 95 dbc f in = 7 0 mhz full 9 4 82 9 4 8 2 dbc f in = 1 39.5 mhz 25c 9 5 9 3 dbc f in = 200 .5 mhz 25c 9 2 89 dbc two - tone intermodulation distortion (imd) ? ain1 and ain2 = 7.0 dbfs f in1 = 70.5 mhz, f in2 = 72.5 mhz 25c 92 92 dbc crosstalk 2 25c 9 7 9 7 db crosstalk (overrange condition) 3 25c 97 97 db power supply rejection ratio (psrr) 4 avdd 25c 4 4 4 3 db drvdd 25c 59 66 db analog in put bandwidth, full power 25c 650 650 mhz 1 see the an - 835 application note , understanding high speed adc testing and evaluation , for definitions and for details on how these tests were completed. 2 crosstalk is measured at 70 mhz with ?1.0 dbfs ana log input on one channel and no input on the adjacent channel. 3 overrange condition is specified with 3 db of the full - scale input range. 4 psrr is measured by injecting a sinusoidal signal at 10 mhz to the power supply pin and measuring the output spur o n the fft. psrr is calculate d as the ratio of the amplitude of the spur voltage over the amplitude of the pin voltage, expressed in decibels (db) .
data sheet ad9635 rev. b | page 5 of 36 digital specificatio ns avdd = 1.8 v, drvdd = 1.8 v, 2 v p - p differential input, 1.0 v internal reference, ain = ?1.0 dbfs, unless otherwise noted. table 3. parameter 1 temp min typ max unit clock inputs (clk+, clk?) logic compliance cmos/lvds/lvpecl differential input voltage 2 full 0.2 3.6 v p -p input voltage range full agnd ? 0.2 avdd + 0.2 v input common - mode voltage full 0.9 v input resistance (differential) 25c 15 k input capacitance 25c 4 pf logic input ( sclk /dfs ) logic 1 voltage full 1.2 avdd + 0. 2 v logic 0 voltage full 0 0.8 v input resistance 25c 30 k input capacitance 25c 2 pf logic input (csb) logic 1 voltage full 1.2 avdd + 0.2 v logic 0 voltage full 0 0.8 v input resistance 25c 26 k input capacitance 25c 2 pf logic input (sdio /pdwn ) logic 1 voltage full 1.2 avdd + 0. 2 v logic 0 voltage full 0 0.8 v input resistance 25c 26 k input capacitance 25c 5 pf logic output (sdio /pdwn ) 3 logic 1 voltage (i oh = 800 a) full 1.79 v logic 0 voltage (i ol = 50 a) full 0.05 v digital outputs (d 0x , d 1x ), ansi -644 logic compliance lvds differential output voltage magnitude (v od ) full 290 345 400 mv output offset voltage (v os ) full 1.15 1.25 1.35 v output coding (default) two s c omplement digital outputs (d0x , d1x ), low power, reduced signal option logic compliance lvds differential output voltage magnitude (v od ) full 160 200 230 mv output offset voltage (v os ) full 1.15 1.25 1.35 v output coding (default) twos c omplement 1 see the an - 835 application note , understanding high speed adc testing and evaluation , for definitions and for details on how these tests were completed. 2 s pecified for lvds and lvpecl only. 3 s pecified for 13 sdio/ pdwn pins sharing the same connection.
ad9635 data sheet rev. b | page 6 of 36 switching specificat ions avdd = 1.8 v, drvdd = 1.8 v, 2 v p - p differential input, 1.0 v internal reference, ain = ?1.0 dbfs, unless otherwise noted. table 4. parameter 1 , 2 temp min typ max unit clock 3 input clock rate full 10 1000 mhz conversion rate 4 full 10 80/125 msps clock pulse width high (t eh ) full 6.25/ 4.00 ns clock pulse width low (t el ) full 6.25/ 4.00 ns output parameters 3 propagation delay (t pd ) full 1.5 2.3 3.1 ns rise time (t r ) (20% to 80%) full 300 ps fall time (t f ) (20% to 80%) full 300 ps fco propagation delay (t fco ) full 1.5 2.3 3.1 ns dco propagation delay (t cpd ) 5 full t fco + (t sample / 12) ns dco to data delay (t data ) 5 full (t sample / 12 ) ? 300 t sample / 12 (t sample / 12 ) + 300 ps dco to fco delay (t frame ) 5 full (t sample / 12 ) ? 300 t sample / 12 (t sample / 12 ) + 300 ps lane delay (t ld ) 90 ps data -to - data skew (t data - max ? t data - min ) full 50 200 ps wake - up time (standby) 25c 250 ns wake -up time (power - down) 6 25c 375 s pipeline latency full 16 clock cycles aperture aperture delay (t a ) 25c 1 ns aperture uncertainty (jitter , t j ) 25c 174 f s rms out - of - range recovery time 25c 1 c lock cycles 1 see the an - 835 application note , understanding high speed adc testing and evaluation , for definitions and for details on how these tests were completed. 2 measured on standard fr - 4 material. 3 can be adjusted via the spi. the conversion rate is the clock rate after the divider. 4 the maximum conversion r ate is based on two - lane output mode. see the digital outputs and timing section for the maximum conversion r ate in one - lane output mode. 5 t sample /1 2 is based on the number of bits in two lvds data lanes. t sample = 1/f s . 6 wake - up time is defined as the time required to return to normal operation from powe r - down mode. timing specifications table 5. parameter description limit unit spi timing requirements see figure 68 t ds setup time between the data and the rising edge of sclk 2 ns min t dh hold time between the data and the rising edge of sclk 2 ns min t clk period of the sclk 40 ns min t s setup time between csb and sclk 2 ns min t h hold time between csb and sclk 2 ns min t high sclk pulse width high 10 ns min t low sclk pulse width low 10 ns min t en_sdio time required for the sdio pin to switch from an input to an output relative to the sclk falling edge (not shown in figure 68) 10 ns min t dis_sdio time required fo r the sdio pin to switch from an output to an input relative to the sclk rising edge (not shown in figure 68) 10 ns min
data sheet ad9635 rev. b | page 7 of 36 timing diagrams refer to the memory map register descriptions section and table 20 for spi register se ttings. figure 2 . 1 2 - bit ddr/sdr, two - lane, 1 frame mode (default) figure 3 . 1 0 - bit ddr/sdr, two - lane, 1 frame mode d0a? d0a+ d1a? d1a+ fco? bytewise mode fco+ d0a? d0a+ d1a? d1a+ fco? dco? clk+ clk? dco+ dco? dco+ fco+ bitwise mode sdr ddr 10577-002 d10 n ? 16 d08 n ? 16 d06 n ? 16 d04 n ? 16 d02 n ? 16 lsb n ? 16 d10 n ? 17 d08 n ? 17 d06 n ? 17 d04 n ? 17 d02 n ? 17 lsb n ? 17 msb n ? 16 d09 n ? 16 d07 n ? 16 d05 n ? 16 d03 n ? 16 d01 n ? 16 msb n ? 17 d09 n ? 17 d07 n ? 17 d05 n ? 17 d03 n ? 17 d01 n ? 17 d05 n ? 16 d04 n ? 16 d03 n ? 16 d02 n ? 16 d01 n ? 16 lsb n ? 16 d05 n ? 17 d04 n ? 17 d03 n ? 17 d02 n ? 17 d01 n ? 17 lsb n ? 17 msb n ? 16 d10 n ? 16 d09 n ? 16 d08 n ? 16 d07 n ? 16 d06 n ? 16 msb n ? 17 d10 n ? 17 d09 n ? 17 d08 n ? 17 d07 n ? 17 d06 n ? 17 t eh t cpd t frame t fco t pd t data t ld t el vinx t a n ? 1 n n + 1 d0a? d0a+ d1a? d1a+ fco? bytewise mode fco+ d0a? d0a+ d1a? d1a+ fco? dco? clk+ clk? dco+ fco+ bitwise mode sdr ddr dco? dco+ 10577-003 d08 n ? 17 d06 n ? 17 d04 n ? 17 d02 n ? 17 lsb n ? 17 d07 n ? 16 d05 n ? 16 d03 n ? 16 d01 n ? 16 msb n ? 17 d07 n ? 17 d05 n ? 17 d03 n ? 17 d04 n ? 16 d03 n ? 16 d02 n ? 16 d01 n ? 16 lsb n ? 16 d04 n ? 17 d03 n ? 17 d02 n ? 17 d01 n ? 17 lsb n ? 17 msb n ? 17 d08 n ? 17 d07 n ? 17 d06 n ? 17 d05 n ? 17 t eh t cpd t frame t fco t pd t data t ld t el vinx t a n ? 1 n n + 1 d08 n ? 16 d06 n ? 16 d04 n ? 16 d02 n ? 16 d08 n ? 15 d06 n ? 15 d04 n ? 15 d02 n ? 15 lsb n ? 16 msb n ? 16 d07 n ? 15 d05 n ? 15 d03 n ? 15 msb n ? 15 d01 n ? 17 d04 n ? 16 d03 n ? 15 d02 n ? 15 d01 n ? 15 d04 n ? 15 msb n ? 16 d08 n ? 16 d07 n ? 16 d06 n ? 16 msb n ? 15 d08 n ? 15 d07 n ? 15 d06 n ? 15 d05 n ? 16
ad9635 data sheet rev. b | page 8 of 36 figure 4 . 1 2 - bit ddr/sdr , two - lane , 2 frame mode figure 5 . 1 0 - bit ddr/sdr , two - lane , 2 frame mode d0a? d0a+ d1a? d1a+ fco? bytewise mode fco+ d0a? d0a+ d1a? d1a+ fco? dco? clk+ clk? dco+ fco+ bitwise mode sdr ddr dco? dco+ 10577-004 d10 n ? 16 d08 n ? 16 d06 n ? 16 d04 n ? 16 d02 n ? 16 lsb n ? 16 d10 n ? 17 d08 n ? 17 d06 n ? 17 d04 n ? 17 d02 n ? 17 lsb n ? 17 msb n ? 16 d09 n ? 16 d07 n ? 16 d05 n ? 16 d03 n ? 16 d01 n ? 16 msb n ? 17 d09 n ? 17 d07 n ? 17 d05 n ? 17 d03 n ? 17 d01 n ? 17 d05 n ? 16 d04 n ? 16 d03 n ? 16 d02 n ? 16 d01 n ? 16 lsb n ? 16 d05 n ? 17 d04 n ? 17 d03 n ? 17 d02 n ? 17 d01 n ? 17 lsb n ? 17 msb n ? 16 d10 n ? 16 d09 n ? 16 d08 n ? 16 d07 n ? 16 d06 n ? 16 msb n ? 17 d10 n ? 17 d09 n ? 17 d08 n ? 17 d07 n ? 17 d06 n ? 17 t eh t cpd t frame t fco t pd t data t ld t el vinx t a n ? 1 n n + 1 d0a? d0a+ d1a? d1a+ fco? bytewise mode fco+ d0a? d0a+ d1a? d1a+ fco? dco? clk+ clk? dco+ fco+ bitwise mode sdr ddr dco? dco+ 10577-005 d08 n ? 17 d06 n ? 17 d04 n ? 17 d02 n ? 17 lsb n ? 17 d07 n ? 16 d05 n ? 16 d03 n ? 16 d01 n ? 16 msb n ? 17 d07 n ? 17 d05 n ? 17 d03 n ? 17 d04 n ? 16 d03 n ? 16 d02 n ? 16 d01 n ? 16 lsb n ? 16 d04 n ? 17 d03 n ? 17 d02 n ? 17 d01 n ? 17 lsb n ? 17 msb n ? 17 d08 n ? 17 d07 n ? 17 d06 n ? 17 d05 n ? 17 t eh t cpd t frame t fco t pd t data t ld t el vinx t a n ? 1 n n + 1 d08 n ? 16 d06 n ? 16 d04 n ? 16 d02 n ? 16 d08 n ? 15 d06 n ? 15 d04 n ? 15 d02 n ? 15 lsb n ? 16 msb n ? 16 d07 n ? 15 d05 n ? 15 d03 n ? 15 msb n ? 15 d01 n ? 17 d04 n ? 16 d03 n ? 15 d02 n ? 15 d01 n ? 15 d04 n ? 15 msb n ? 16 d08 n ? 16 d07 n ? 16 d06 n ? 16 msb n ? 15 d08 n ? 15 d07 n ? 15 d06 n ? 15 d05 n ? 16
data sheet ad9635 rev. b | page 9 of 36 figure 6 . wordw ise ddr, one - lane, 1 frame, 1 2 - bit output mode figure 7 . wordw ise ddr, one - lane, 1 frame, 1 0 - bit output mode 10577-006 d0x? d0x+ fco? dco+ clk+ vinx clk? dco? fco+ d10 n ? 17 msb n ? 17 d9 n ? 17 d8 n ? 17 d7 n ? 17 d6 n ? 17 d5 n ? 17 d4 n ? 17 d3 n ? 17 d2 n ? 17 d1 n ? 17 d0 n ? 17 msb n ? 16 d10 n ? 16 t a t data t eh t fco t frame t pd t cpd t el n ? 1 n 10577-007 d0x? d0x+ fco? dco+ clk+ vinx clk? dco? fco+ msb n ? 9 d8 n ? 9 d8 n ? 8 d7 n ? 8 d6 n ? 8 d7 n ? 9 d6 n ? 9 d5 n ? 9 d4 n ? 9 d3 n ? 9 d2 n ? 9 d1 n ? 9 d0 n ? 9 msb n ? 8 d5 n ? 8 t a t data t eh t fco t frame t pd t cpd t el n ? 1 n
ad9635 data sheet rev. b | page 10 of 36 absolute maximum rat ings table 6. parameter rating electrical avdd to agnd ? 0.3 v to +2.0 v drvdd to agnd ? 0.3 v to +2.0 v digital outputs to agnd (d0 x , d1 x , dco+, dco?, fco+, fco?) ? 0.3 v to +2.0 v clk+, clk? to agnd ? 0.3 v to +2.0 v vin x +, vin x ? to agnd ? 0.3 v to +2.0 v sclk /d fs , sdio / pdwn , csb to agnd ? 0.3 v to +2.0 v rbias to agnd ? 0.3 v to +2.0 v vref to agnd ? 0.3 v to +2.0 v v cm to agnd ? 0.3 v to +2.0 v environmental operating temperature range (ambient) ? 40 c to +85 c maximum junction temperature 150c lead temperature (soldering, 10 sec) 300c storage temperature range (ambient) ? 65c to +150 c stresses at or above those listed under absolute maximum ratings may cause permanent damage to the product. this is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. operation beyond the maximum op erating conditions for extended periods may affect product reliability. thermal resistance the exposed paddle i s the only ground connection on the chip. the exposed paddle must be soldered to the agnd plane of the users circuit board. soldering the exposed paddle to the users board also increases the reliability of the solder joints and maximizes the thermal capability of the package. table 7 . thermal resistance package type airflow velocity (m/sec) ja 1, 2 jc 1, 3 jb 1, 4 32 - lead lfcsp , 5 mm 5 mm 0 37.1 3.1 20.7 0.3 c/w 1.0 32.4 0.5 c/w 2.5 29.1 0.8 c/w 1 per jedec jesd 51- 7, plus jedec jesd 51- 5 2s2p test board. 2 per jedec jesd51 - 2 (still air) or jedec jesd51 - 6 (moving air). 3 per mil - s td 883, method 1012.1. 4 per jedec jesd51 - 8 (still air). typical ja is specified for a 4 - layer pcb with a solid ground plane. as shown in table 7 , airflow improves heat dissipation, which reduces ja . in addition, metal in direct contact with the package leads from metal traces, through holes, ground, and power planes reduces the ja . esd caution
data sheet ad9635 rev. b | page 11 of 36 pin configuration an d function descripti ons figure 8 . pin configuration, top view table 8 . pin function descriptions pin no. mnemonic description 0 agnd , exposed pad the exposed paddle is the only ground connection on the chip. it must be soldered to the analog ground of the pcb to ensure proper functionality and heat dissipation, noise, and mechanical strength benefits. 1, 24, 25, 28 29, 32 avdd 1.8 v supply pin s for adc analog core domain. 2, 3 clk+, clk ? differential encode clock for lv pecl, lvds, or 1.8 v cmos inputs. 4 sdio/pdwn data input/output in spi mode (sdio). bidirectional spi data i/o with 30 k internal pull - down. power - down in non - spi mode (pdwn). static control of chip power - down with 30 k internal pull - down. 5 sclk/dfs spi clock input in spi mode (sclk). 30 k internal pull - down. data format select in non - spi mode (dfs). stati c control of data output format, with 30 k internal pull - down. dfs high = two s complement output; dfs low = offset binary output. 6, 19 drvdd 1.8 v supply pins for output driver domain. 7, 8 d1b ? , d1b+ channel b digital outputs. 9, 10 d0b ? , d0b+ channel b digital outputs. 11, 12 dco ? , dco+ data clock outputs. 13, 14 fco ? , fco+ frame clock outputs. 15, 16 d1a ? , d1a+ channel a digital outputs. 17, 18 d0a ? , d0a+ channel a digital outputs. 20 csb spi chip select. active low enable with 15 k internal pull - up. 21 vref 1.0 v voltage reference output. 22 vcm analog output voltage at mid avdd s upply. sets the common - mode voltage of the analog inputs. 23 rbias set s the analog current b ias. connect this pin to a 10 k (1% tolerance) resistor to ground. 26, 27 v ina?, v ina+ channel a adc analog inputs. 30, 31 vinb+, v inb ? channel b adc analog inputs. 24 a vdd 23 rbias 22 vcm 21 vref 20 csb 19 dr vdd 18 d0a+ 17 d0a? 1 2 3 4 5 6 7 8 a vdd clk+ clk? sdio/pdwn sclk/dfs dr vdd d1b? d1b+ 9 10 1 1 12 13 14 15 16 d0b? d0b+ dco? dco+ fco? fco+ d1a? d1a+ 32 31 30 29 28 27 26 25 a vdd vinb? vinb+ a vdd a vdd vina+ vina? a vdd ad9635 top view (not to scale) notes 1. the exposed paddle is the only ground connection on the chip. it must be soldered to the analog ground of the pcb to ensure proper functionality and heat dissipation, noise, and mechanical strength benefits. 10577-008
ad9635 data sheet rev. b | page 12 of 36 typical performance characteristics ad963 5 -80 figure 9 . single - tone 16k fft with f in = 9.7 mhz, f sample = 80 msps figure 10 . single - tone 16k fft with f in = 30.5 mh z , f sample = 80 msps figure 11 . single - tone 16k fft with f in = 70 .2 mhz, f sample = 80 msps figure 12 . single - tone 16k fft with f in = 139.5 mhz, f sample = 80 msps figure 13 . single - tone 16k fft with f in = 200 .5 mhz, f sample = 80 msps figure 14 . single - tone 16k fft with f in = 200 .5 mhz, f sample = 80 msps , c lock d ivide = divide - by - 8 0 ?140 ?120 ?100 ?80 ?60 ?40 ?20 0 10 20 30 40 amplitude (dbfs) frequency (mhz) 80msps 9.7mhz at ?1dbfs snr = 70.7db (71.7dbfs) sfdr = 92.9dbc 10577-009 0 ?140 ?120 ?100 ?80 ?60 ?40 ?20 0 10 20 30 40 amplitude (dbfs) frequency (mhz) 80msps 30.5mhz at ?1dbfs snr = 70.6db (71.6dbfs) sfdr = 91.2dbc 10577-010 0 ?140 ?120 ?100 ?80 ?60 ?40 ?20 0 10 20 30 40 amplitude (dbfs) frequency (mhz) 80msps 70.2mhz at ?1dbfs snr = 70.3db (71.3dbfs) sfdr = 93.5dbc 10577-0 1 1 0 ?140 ?120 ?100 ?80 ?60 ?40 ?20 0 10 20 30 40 amplitude (dbfs) frequency (mhz) 80msps 139.5mhz at ?1dbfs snr = 68.8db (69.8dbfs) sfdr = 80.9dbc 10577-012 0 ?140 ?120 ?100 ?80 ?60 ?40 ?20 0 10 20 30 40 amplitude (dbfs) frequency (mhz) 80msps 200.5mhz at ?1dbfs snr = 67.4db (68.4dbfs) sfdr = 83dbc 10577-013 0 ?15 ?30 ?45 ?60 ?75 ?105 ?90 ?120 ?135 0 8 4 12 16 28 20 24 32 40 36 amplitude (dbfs) frequency (mhz) 80msps 200.5mhz at ?1dbfs snr = 68.8db (69.8dbfs) sfdr = 81.3dbc 10577-014
data sheet ad9635 rev. b | page 13 of 36 figure 15 . snr/sfdr vs. analog input level; f in = 9.7 mhz, f sample = 80 msps figure 16 . two - tone 16k fft with f in1 = 70.5 mhz and f in2 = 72.5 mhz, f sample = 80 msps figure 17 . two - tone sfdr/imd3 vs. input amplitude (ain) with f in1 = 70.5 mhz and f in2 = 72.5 mhz, f sample = 80 msps figure 18 . snr/sfdr vs. f in ; f sample = 80 msps figure 19 . snr/sfdr vs. temperature; f in = 9.7 mhz, f sample = 80 msps figure 20 . inl; f in = 9.7 mhz, f sample = 80 msps 120 ?20 ?90 0 snr/sfdr (dbfs/dbc) input amplitude (dbfs) sfdrfs sfdr snrfs snr 0 20 40 60 80 100 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 10577-015 0 ?140 ?120 ?100 ?80 ?60 ?40 ?20 0 10 20 30 40 amplitude (dbfs) frequency (mhz) 10577-016 ain1 and ain2 = ?7dbfs sfdr = 91.4dbc imd2 = ?92.6dbc imd3 = ?92.3dbc 0 ?20 ?40 ?60 ?80 ?100 ?120 ?90 ?10 ?30 ?50 ?70 sfdr/imd3 (dbc/dbfs) input amplitude (dbfs) sfdr (dbc) sfdr (dbfs) imd3 (dbc) imd3 (dbfs) 10577-017 110 0 0 260 snr/sfdr (dbfs/dbc) input frequency (mhz) 70 10 20 30 40 50 60 80 90 100 100 120 140 80 20 40 60 240 160 180 200 220 sfdr snr 10577-018 120 0 ?40 ?20 0 20 40 60 80 snr/sfdr (dbfs/dbc) temperature (c) 10 20 30 40 50 60 70 80 90 100 110 sfdr snr 10577-019 0.30 ?0.25 1 inl (lsb) output code ?0.20 ?0.15 0.15 0.10 0.05 ?0.05 ?0.10 0 0.25 0.20 357 713 1069 1425 1781 2137 2493 2849 3205 3561 3917 4273 10577-020
ad9635 data sheet rev. b | page 14 of 36 figure 21 . dnl ; f in = 9.7 mhz, f sample = 80 msps figure 22 . input referred noise histogram; f sample = 80 msps figure 23 . psrr vs. frequency; f clk = 125 mhz, f sample = 80 msps figure 24 . snr/sfdr vs. sample rate ; f in = 9.7 mhz, f sample = 80 msps figure 25 . snr/sfdr vs. sample rate ; f in = 70 mhz, f sample = 80 msps 0.25 ?0.15 1 dnl (lsb) output code ?0.10 ?0.05 0 0.20 0.15 0.10 0.05 4273 357 713 1069 1425 1781 2137 2493 2849 3205 3561 3917 10577-021 2,500,000 2,000,000 1,500,000 1,000,000 500,000 0 1 2 3 5 4 7 6 number of hits code 0.41lsb rms 10577-022 90 0 1 10 psrr (db) frequency (mhz) 10 20 30 40 50 60 70 80 drvdd avdd 10577-023 110 0 10 50 30 70 90 snr/sfdr (dbfs/dbc) sample rate (msps) 10 20 30 40 60 50 70 90 80 100 sfdr snrfs 10577-024 110 0 10 20 30 40 60 50 70 90 80 100 10 50 30 70 90 snr/sfdr (dbfs/dbc) sample rate (msps) sfdr snrfs 10577-025
data sheet ad9635 rev. b | page 15 of 36 ad963 5 - 125 figure 26 . single - tone 16k fft with f in = 9.7 mhz, f sample = 125 msps figure 27 . single - tone 16k fft with f in = 30.5 mh z , f sample = 125 msps figure 28 . single - tone 16k fft with f in = 70 .2 mhz, f sample = 125 msps figure 29 . single - tone 16k fft with f in = 1 39.5 mhz, f sample = 125 msps figure 30 . single - tone 16k fft with f in = 200 .5 mhz, f sample = 125 msps figure 31 . single - tone 16k fft with f in = 200 .5 mhz, f sample = 12 5 msps , clock d ivide = divide - by - 8 0 ?140 ?120 ?100 ?80 ?60 ?40 ?20 0 20 40 60 amplitude (dbfs) frequency (mhz) 125msps 9.7mhz at ?1dbfs snr = 70.6db (71.6dbfs) sfdr = 93.3dbc 10577-026 0 ?140 ?120 ?100 ?80 ?60 ?40 ?20 0 20 40 60 amplitude (dbfs) frequency (mhz) 125msps 30.5mhz at ?1dbfs snr = 70.5db (71.5dbfs) sfdr = 92dbc 10577-027 0 ?140 ?120 ?100 ?80 ?60 ?40 ?20 0 20 40 60 amplitude (dbfs) frequency (mhz) 125msps 70.2mhz at ?1dbfs snr = 70.1db (71.1dbfs) sfdr = 93.6dbc 10577-028 0 ?140 ?120 ?100 ?80 ?60 ?40 ?20 0 20 40 60 amplitude (dbfs) frequency (mhz) 125msps 139.5mhz at ?1dbfs snr = 69.1db (70.1dbfs) sfdr = 92.9dbc 10577-029 0 ?140 ?120 ?100 ?80 ?60 ?40 ?20 0 20 40 60 amplitude (dbfs) frequency (mhz) 125msps 200.5mhz at ?1dbfs snr = 67.8db (68.8dbfs) sfdr = 82.4dbc 10577-030 0 ?15 ?30 ?45 ?60 ?75 ?105 ?90 ?120 ?135 0 6 12 18 24 30 36 48 54 60 42 amplitude (dbfs) frequency (mhz) 125msps 200.5mhz at ?1dbfs snr = 68.6db (69.6dbfs) sfdr = 81.9dbc 10577-031
ad9635 data sheet rev. b | page 16 of 36 figure 32 . snr/sfdr vs. analog input level; f in = 9.7 mhz, f sample = 125 msps figure 33 . two - tone 16k fft with f in1 = 70.5 mhz and f in2 = 72.5 mhz, f sample = 125 msps figure 34 . two - tone sfdr/imd3 vs. input amplitude (ain) with f in1 = 70.5 mhz and f in2 = 72.5 mhz, f sample = 125 msps figure 35 . snr/sfdr vs. f in ; f sample = 125 msps figure 36 . snr/sfdr vs. temperature; f in = 9.7 mhz, f sample = 125 msps figure 37 . inl; f in = 9.7 mhz, f sample = 125 msps 120 ?20 ?90 0 snr/sfdr (dbfs/dbc) input amplitude (dbfs) sfdrfs sfdr snrfs snr 0 20 40 60 80 100 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 10577-032 0 ?140 ?120 ?100 ?80 ?60 ?40 ?20 0 20 40 60 amplitude (dbfs) frequency (mhz) 10577-033 ain1 and ain2 = ?7dbfs sfdr = 89.1dbc imd2 = ?93.9dbc imd3 = ?91.6dbc 0 ?20 ?40 ?60 ?80 ?100 ?120 ?90 ?10 ?30 ?50 ?70 sfdr/imd3 (dbc/dbfs) input amplitude (dbfs) sfdr (dbc) sfdr (dbfs) imd3 (dbc) imd3 (dbfs) 10577-034 110 0 0 260 snr/sfdr (dbfs/dbc) input frequency (mhz) 70 10 20 30 40 50 60 80 90 100 100 120 140 80 20 40 60 240 160 180 200 220 sfdr snr 10577-035 120 0 ?40 ?20 0 20 40 60 80 snr/sfdr (dbfs/dbc) temperature (c) 10 20 30 40 50 60 70 80 90 100 110 snr sfdr 10577-071 0.4 ?0.4 1 inl (lsb) output code ?0.3 ?0.2 ?0.1 0 0.1 0.2 0.3 343 685 1027 1369 1711 2053 2395 2737 3079 3421 3763 4105 10577-072
data sheet ad9635 rev. b | page 17 of 36 figure 38 . dnl; f in = 9.7 mhz, f sample = 125 msps figure 39 . input - referred noise histogram ; f sample = 125 msps figure 40 . psrr vs. frequency; f clk = 125 mhz , f sample = 125 msps figure 41 . snr/sfdr vs. sample rate ; f in = 9.7 mhz , f sample = 125 msps figure 42 . snr/sfdr vs. sample rate ; f in = 70 mhz , f sample = 125 msps 1 343 685 1027 1369 1711 2053 2395 2737 3079 3421 3763 4105 0.25 ?0.15 dnl (lsb) output code ?0.10 ?0.05 0 0.20 0.15 0.10 0.05 10577-073 2,500,000 500,000 1,000,000 1,500,000 2,000,000 0 n ? 3 n ? 2 n ? 1 n + 1 n + 2 n + 3 n number of hits code 0.42lsb rms 10577-076 90 0 1 10 psrr (db) frequency (mhz) 10 20 30 40 50 60 70 80 drvdd avdd 10577-077 110 0 10 20 30 40 60 50 70 90 80 100 10 50 30 70 90 130 110 snr/sfdr (dbfs/dbc) sample rate (msps) sfdr snrfs 10577-074 110 0 10 20 30 40 60 50 70 90 80 100 10 50 30 70 90 130 110 snr/sfdr (dbfs/dbc) sample rate (msps) snrfs sfdr 10577-075
ad9635 data sheet rev. b | page 18 of 36 equivalent circuits figure 43 . equivalent analog input circuit figure 44 . equivalent clock input circuit figure 45 . equivalent sdio/ pdwn input circuit figure 46 . equivalent digital output circuit figure 47 . equivalent sclk /d fs input circuit figure 48 . equivalent rbias and vcm circuit figure 49 . equivalent csb input circuit figure 50 . equivalent vref circuit a vdd vinx 10577-036 clk+ clk? 0.9v 15k? 10? 10? 15k? a vdd a vdd 10577-037 31k? sdio/pdwn 400? dr vdd 10577-038 d r vdd d0x?, d1x? d0x+, d1x+ v v v v 10577-039 400? d r vdd 30k? sclk/dfs 10577-040 rbias and vcm 400? a vdd 10577-041 csb 400? d r vdd 15k? 10577-042 vref a vdd 7.5k? 400? 10? 10577-043
data sheet ad9635 rev. b | page 19 of 36 theory of operation the ad963 5 is a multistage, pipelined adc . each stage provides sufficient overlap to correct for flash errors in the preceding stage. the quantized outputs from each st age are combined into a final 12 - bit result in the digital correction logic. the pipelined architecture allow s the first stage to operate with a new input sample while the remaining stages operate with the preceding samples. sampling occurs on the rising edge of the clock. each stage of the pipeline, excluding the last, consists of a low resolution flash adc connected to a switched - capacitor dac and an interstage residue amplifier (for example, a multiplying digital - to - analog converter (mdac)). the residue amplifier magnifies the diffe rence between the reconstructed dac output and the flash input for the next stage in the pipeline. one bit of redundancy is used in each stage to facilitate digital correction of flash errors. the last stage consists of a flash adc. the output staging bloc k aligns the data, corrects errors, and passes the data to the output buffers. the data is then serialized and aligned to the frame and data clocks. analog input conside rations the analog input to the ad963 5 is a differential switched - capacitor circuit designed for processing differential input signals. this circuit can support a wide common - mode range while maintaining excellent performance. by using an input common - mode voltage of midsupply, users can minimize signal - dependent errors and achieve optimum performance. figure 51 . switched - capacitor input circuit the clock signal alternately switches the input circuit between samp le mode and hold mode (see figure 51 ). when the input circuit is switched to sample mode, the signal source must be capable of charging the sample capacitors and s ettling within one - half of a clock cycle. a small resistor in series with each input can help reduce the peak transient current injected from the output stage of the driving source. in addition, low q inductors or ferrite beads can be placed on each leg of the input to reduce high differential capacitance at the analog inputs and , therefore , achieve the maximum bandwidth of the adc. such use of low q inductors or ferrite beads is required when driving the converter front end at high if freque ncies. either a differential capacitor or two single - ended capacitors can be placed on the inputs to provide a matching passive network. this ultimately creates a low - pass filter at the input to limit unwanted broadband noise. see the an - 742 application note , the an - 827 application note , and the analog dialogue article transformer - coupled front - end for wideband a/d converters (volume 39, april 2005) for more information . in general, the precise values depend on the application. input common mode the analog inputs of the ad963 5 are not internally dc - biased. therefore, in ac - coupled applications, the user must provide this bias externally. setting the device so that v cm = avdd /2 is recommended for optimum performance, but the device can function over a wider range with reasonable performance, as shown in figure 52. figure 52 . snr/sfdr vs. input common - mode voltage, f in = 9.7 mhz, f sample = 125 msps an on - chip, common - mode voltage reference is included in the design and is available from the vcm pin. the vcm pin must be decoupled to ground by a 0.1 f capacitor, as described in the applications information section. maximum snr performance is achieved by setting the adc to the largest span in a differential configuration. in t he case of the ad963 5 , the largest i nput span available is 2 v p - p. s s h c par c sample c sample c par v i nx? h s s h v i nx+ h 10577-044 100 20 0.5 1.3 snr/sfdr (dbfs/dbc) input common mode (v) 30 40 50 60 70 80 90 0.6 0.7 0.8 0.9 1.0 1.1 1.2 sfdr snrfs 10577-078
ad9635 data sheet rev. b | page 20 of 36 differential input configurations there are several ways to drive the ad963 5 either actively or passively. however, optimum performance is achieved by driving the analog input s differentially. using a d ifferential double ba lun configuration t o drive the ad963 5 provides excellent perfor mance and a flexible interface to the adc for baseband app lications (see figure 55). for applications where snr is a key parameter, differential trans - former coupling is the recommended input configuration (see figure 56) because the noise performance of most amplifiers is not adequate to achieve the true performance of the ad963 5 . regardless of the configuration, the value of the shunt capacitor, c, is dependent on the input frequency and may need to be reduced or removed. it is not recommended to drive the ad963 5 input s single - ended. voltage reference a stable and accurate 1.0 v voltage r eference is built into the ad963 5 . the vref pin should be externally decoupled to ground with a low esr, 1.0 f capacitor in parallel with a low esr, 0.1 f ceramic capacitor. figure 53 shows how the internal reference voltage is affected by loading. figure 54 shows t he typical drift characteristics of the internal reference in 1.0 v mode. the internal buffer generates the positive and negative full - scale references for the adc core. figure 53 . v ref error vs. l oad current figure 54 . typical v ref drift figure 55 . differential double balun input configuration for baseband applications figure 56 . differential transformer - coupl ed configuration for baseband applications 0 ?0.5 ?1.0 ?1.5 ?2.0 ?2.5 ?3.0 ?3.5 ?4.0 ?4.5 ?5.0 0 3.0 2.5 2.0 1.5 1.0 0.5 v ref error (%) load current (ma) interna l v ref = 1v 10577-048 4 ?8 ?40 85 v ref error (mv) temperature (c) ?6 ?4 ?2 0 2 ?15 10 35 60 10577-049 adc r 0.1f 0.1f 2v p-p vcm c *c1 *c1 c r 0.1f 0.1f 0.1f 33? 200? 33? 33? 33? vinx+ vinx? et1-1-i3 c c 5pf r *c1 is optional 10577-046 2v p-p r r *c1 *c1 is optional 49.9 0.1f adt1-1wt 1:1 z ratio vinx? adc vinx+ *c1 c vcm 33? 33? 200? 0.1f 5pf 10577-047
data sheet ad9635 rev. b | page 21 of 36 clock input consider ations for optimum performance, clock the ad963 5 sample clock inputs, clk+ and clk?, with a d ifferential signal. the signal is typically ac - coupled into the clk+ and clk? pins via a transformer or capacitors. th ese pins are biased internally (see figure 44 ) and require no external bias. clock input options th e ad963 5 has a flexible clock input structure. the cl ock in put can be a cmos, lvds, lvpecl, or sine wave signal. regardless of the type of signal being used, clock source jitter is of the most concern, as described in the jitter considerations section. figure 57 and figure 58 show two preferred methods for clock ing the ad963 5 (at clock rates up to 1 ghz prior t o the internal clock divider). a low jitter clock source is converted from a single - ended signal to a differential signal using either an rf transformer or an rf balun. figure 57 . transformer - coupled dif ferential clock (up to 200 mhz) figure 58 . balun - coupled differential clock (up to 1 ghz) the rf balun configuration is recommended for clock frequencies between 125 mhz and 1 ghz, and the rf transformer configu - ration is recom mended for clock frequencies from 10 mhz to 200 mhz. the back - to - back schottky diodes across the transformer/balun secondary winding limit clock excursions into the ad9 635 to approximately 0.8 v p - p differential. this limit helps prevent the large voltage swings of the clock from feeding through to other portions of the ad963 5 while preserving the fast rise and fall times of the signal that are critical to achieving low jitter performance. however, the diode capacitance comes into play at frequencies above 500 mhz. care must be taken when choosing the appropriate sign al limiting diode. if a low jitter clock source is not available, another option is to ac couple a differential pecl signal to the sample clock input pins, as shown in figure 59 . the ad9510/ ad9511 / ad9512 / ad9513 / ad9514 / ad9515 / ad9516 - 0 / ad9516 - 1 / ad9516 - 2 / ad9516 - 3 / ad9516 - 4 / ad9516 - 5 / ad9517 - 0 / ad9517 - 1 / ad9517 - 2 / ad9517 - 3 / ad9517 - 4 clock drivers of fer excellent jitter performance. figure 59 . differential pecl sample clock (up to 1 ghz) a third option is to ac couple a differential lvds signal to the sample clock input pins, as shown in figure 60 . the ad9510 / ad9511 / ad9512 / ad9513 / ad9514 / ad9515 / ad9516 - 0 / ad9516 - 1 / ad9516 - 2 / ad9516 - 3 / ad9516 - 4 / ad9516 - 5 / ad9517 - 0 / ad9517 - 1 / ad9517 - 2 / ad9517 - 3 / ad9517 - 4 clock drivers offer excellent jitter performance. figure 60 . differential lvds sample clock (up to 1 ghz) in some applications, it may be acceptable to drive the sample clock inputs with a single - ended 1.8 v cmos signal. in such applica - tions, drive the clk+ pin directly from a cmos gate, and bypass the clk? pin to ground with a 0.1 f capacitor (see figure 61). figure 61 . single - ended 1.8 v cmos input clock (up to 200 mhz ) input clock divider the ad963 5 contains an input clock divider that can divide the input clock by integer values from 1 to 8. to achieve a given sample rate, the frequency of the externally applied clock must be multi - plied by the divide value. the increased rate of the external clock normally results in lower clock jitter, which is beneficial for if undersampling applications. 0.1f 0.1f 0.1f 0.1f schottky diodes: hsms2822 clock input 50? 100? clk? clk+ adc mini-circuits ? adt1-1wt, 1:1 z xfmr 10577-050 0.1f 0.1f 0.1f clock input 0.1f 50? clk? clk+ schottky diodes: hsms2822 adc 10577-051 10 0? 0.1f 0.1f 0.1f 0.1f 240? 240? 50k? 50k? clk? clk+ clock input clock input adc ad951x pecl driver 10577-053 10 0? 0.1f 0.1f 0.1f 0.1f 50k? 50k? clk? clk+ adc clock input clock input ad951x lvds driver 10577-054 optional 100? 0.1f 0.1f 0.1f 50? 1 1 50? resistor is optional. clk? clk+ adc v cc 1k? 1k? clock input ad951x cmos driver 10577-055
ad9635 data sheet rev. b | page 22 of 36 clock duty cycle typical high speed adcs use both clock edges to generate a vari ety of internal timing signals and, as a result, may be sensitive to the clock duty cycle. commonly, a 5% tolerance is required on the clock duty cycle to maintain dynamic performance characteristics. the ad963 5 contains a duty cycle stabilizer (dcs) that retimes the nonsampling (falling) edge, providing an internal clock signal with a nominal 50% duty cycle. this allows the user to provide a wide range of clock input duty cycles without affecting the perfor mance of the ad963 5 . noise and distortion performance are nearly flat for a wide range of duty cycles with the dcs on . jitter in the rising edge of the input is still of concern and is not easily reduced by the internal stabilization circuit. the duty cycle control loop does not function for clock rates of less than 20 mhz, nominally. the loop has a time constant associated with it that must be considered in applications in which the clock rate can change dynamically. a wait time of 1.5 s to 5 s is required after a dynamic clock frequency increase or decrease before the dc s loop is relocked to the input signal. jitter considerations high speed, high resolution adcs are sensitive to the quality of the clock input. the degradation in snr at a given input frequency ( f a ) due only to aperture jitter ( t j ) can be calculated by the following equation: snr degradation = 20 log 10 ? ? ? ? ? ? ? ? j a t f 2 1 in this equation, the rms aperture jitter represents the root mean square of all jitter sources, including the clock input, analog input signal, and adc aperture jitter specification s. if undersampling applications are particularly sensitive to jitter (see figure 62). figure 62 . ideal snr vs. input frequency and jitter the clock input should be treated as an analog signal in cases where aperture jitter may affect the dynamic ra nge of the ad963 5 . power supplies for clock drivers should be separated from the adc output driver supplies to avoid modulating the clock signal with d igital noise. low jitter, crystal - controlled oscillators make the best clock sources. if the clock is generated from another type of source (by gating, dividing, or other methods), it should be retim ed by the original clock as the last step. refer to the an - 501 application note and the an - 756 application note for more in - depth information about jitter performance as it r elates to adcs. pow er dissipation and p ower - down mode as shown in figure 63, the power dissipated by the ad963 5 is proportional to its sample rate. the ad963 5 is placed in power - down mode either by the spi port or by asserting t he pdwn pin high. in this state, the adc typically dissipates 2 mw. during power - down, the output drivers are placed in a high impedance state. asserting the pdwn pin low returns the ad963 5 to its normal operating mode. note that pdwn is referenced to the digital output driver supply (drvdd) and should not exceed that supply voltage. figure 63 . total power dissipation vs. f sample for f in = 9.7 mhz low power dissipation in power - down mode is achieved by shutting down the reference, reference buffer, biasing networks, and clock. internal capacitors are discharged when the part ent ers power - down mode and must then be recharged when the part returns to normal operation. as a result, wake - up time is related to the time spent in power - down mode, and shorter power - down cycles result in proportionally shorter wake - up times. when using the spi port interface, the user can place the ad c in power - down mode or standby mode. standby mode allows the user to keep the internal reference circuitry powered when faster wake - up times are required. see the memory map section for more details on using these features. 1 10 100 1000 16 b i t s 14 b i t s 12 b i t s 30 40 50 60 70 80 90 100 1 10 120 130 0.125ps 0.25ps 0.5ps 1.0ps 2.0ps a n a l og i npu t f reque n cy (m h z) 10 bits 8 bits rms clock jitter requirement snr (db) 10577-056 240 180 200 220 160 140 120 100 10 130 total power dissipation (mw) sample rate (msps) 30 50 70 90 110 50msps 80msps 125msps 40msps 20msps 65msps 105msps 10577-079
data sheet ad9635 rev. b | page 23 of 36 digital outputs and timing the ad96 3 5 differential outputs conform to the ansi - 644 lvds standard on default power - up. this default setting can be changed to a low power, reduced signal option (similar to the ieee 1596.3 standard) via the spi. the lvds driver current is derived on chip and s ets t he output current at eac h output equal to a nominal 3.5 ma. a 100 ? differential termination resistor placed at the lvds receiver inputs results in a nominal 350 mv swing (or 700 mv p - p differential) at the receiver. when operating in reduced range mode, the output current is reduced to 2 ma. this results in a 200 mv swing (or 400 mv p - p differential) across a 100 ? termination at the receiver. the lvds outputs facilitate interfacing with lvds receivers in custom asics and fpgas for su perior switching performance in noisy environments. single point - to - point net topologies are recommended with a 100 ? termination resistor placed as close as possible to the receiver . if there is no far - end receiver termi - nation or there i s poor differential trace routing, timing errors may result. to avoid such timing errors, ensure that the trace length is less than 24 inches and that the differential output traces are close together and at equal lengths. figur e 64 shows an example of the fco and data stream with proper trace length and position . figure 64. ad9635 - 125 , lvds output timing example in ansi - 644 mode (default) figure 65 shows the lvds output timing example in reduced range mode. figure 65. ad9635 - 125 , lvds output timin g example in reduced range mode figure 66 shows a n example of the lvds output using the a nsi - 644 standard (default) data eye and a time interval error (tie) jitter histogram with trace lengths of less than 24 inches on standard fr - 4 material . figure 66 . data eye for lvds outputs in ansi - 644 mode with trace lengths of less t han 24 inches on standard fr - 4 material, external 100 ? far - end termination only d0 500mv/div d1 500mv/div dco 500mv/div fco 500mv/div 4ns/div 10577-058 d0 400mv/div d1 400mv/div dco 400mv/div fco 400mv/div 4ns/div 10577-059 6k 7k 1k 2k 3k 5k 4k 0 200ps 250ps 300ps 350ps 400ps 450ps 500ps tie jitter histogram (hits) 500 400 300 200 100 ?500 ?400 ?300 ?200 ?100 0 ?0.8ns ?0.4ns 0ns 0.4ns 0.8ns eye diagram voltage (mv) eye: all bits uls: 7000/400354 10577-060
ad9635 data sheet rev. b | page 24 of 36 figure 67 shows an example of trace lengths exceeding 24 inches o n standard fr - 4 material. note that the tie jitter histogram reflects the decrease of the data eye opening as the edge dev iates from the ideal position. figure 67 . data eye for lvds outputs in ansi - 644 mode wi th trace lengths greater t han 24 inches on standard fr - 4 material, external 100 ? far - end termination only it is the re spon sibility of the user to determine if the waveforms meet the timing budget of the design w hen the trace lengths exceed 24 inches. additional spi options allow the user to further increase the internal termination (increasing the current) of both outputs to drive longer trace lengths. this increase in current can be achieved by programming register 0x15. although an increase in current produces sharper rise and fall times on the data edges and is less prone to bit errors, the power dissipation of the drvdd supply increases when this option is use d. the format of the output data is two s compl e ment by default. an example of the output coding format can be found in table 9 . to change the output data format to offset binary, see the memory map section. data from each adc is serialized and provided on a separate channel in two lanes in ddr mode . the data rate for each serial stream is equal to ( 12 bits the sample clock rate )/2 lanes, with a maximum of 750 mbps/lane ( ( 12 bits 125 msps ) / ( 2 lanes ) = 750 mbps /lane ) ) . the maximum allowable output data rate is 1 gbps/lane. if one - lane mode is used , the data rate double s for a given sample rate. to stay within the maximum data rate of 1 gbps/lane, the sample rate is limited to a maximum of 83.3 msps in one - lane output mode. the lowest typical conversion rate is 10 msps. for conversion rates of less than 20 msps , the spi must be used to reconfigure the integrated pll. see register 0x21 in the memory map section for details on enabling this feature. two output cl ocks are provided to assist in capturing data from the ad963 5 . the dco is used to clock the output data and is equal to 3 the sample clock (clk) rate for the default mode of operation . data is clocked out of the ad963 5 and must be captured on the rising and falling edges of the dco that supports dou ble data rate (ddr) capturing. the fco is used to signal the start of a new output byte and is equal to the sample clock rate in 1 frame mode . see the timing diagrams section for more information. when the spi is used, the dco phase can be adjusted in 60 increments relative to the data edge. this enables the user to refine system timing margins , if required. the default dco+ and dco? timing, as shown in figure 2 , is 18 0 relative to the output data edge. a 1 0 - bit serial stream can also be initiated from the spi. this allows the user to implement and test compatibility to lower resolution systems. when changing the resolution to a 1 0 - bit serial stream, the data stream is shortened. in default mode, as shown in figure 2 , the msb is first in the data output serial stream. this can be inverted , by using the spi , so that the lsb is first in the data output serial stream. table 9 . digital output coding input (v) condition (v) offset binary output mode two s complement mode vin+ ? vin? < ? vref ? 0.5 lsb 0000 0000 0000 1000 0000 0000 vin+ ? vin? ? vref 0000 0000 0000 1000 0000 0000 vin+ ? vin? 0 v 1000 0000 0000 0000 0000 0000 vin+ ? vin? +vref ? 1.0 lsb 1111 1111 1111 0111 1111 1111 vin+ ? vin? >+vref ? 0.5 lsb 1111 1111 1111 0111 1111 1111 500 400 300 200 100 ?500 ?400 ?300 ?200 ?100 0 ?0.8ns ?0.4ns 0ns 0.4ns 0.8ns eye diagram voltage (mv) eye: all bits uls: 8000/414024 10k 12k 2k 4k 6k 8k 0 ?800ps ?600ps ?400ps ?200ps 0ps 200ps 400ps 600ps tie jitter histogram (hits) 10577-061
data sheet ad9635 rev. b | page 25 of 36 table 10 . flexible output test modes output test mode bit sequence pattern name digital output word 1 digital output word 2 subject to data format select notes 0000 off (default) n ot applicable n ot applicable n/a 0001 midscale short 10 0000 0000 (1 0- bit) 1000 0000 0000 (1 2 - bit) n ot applicable yes offset binary code shown 0010 +full - scale short 11 1111 1111 (1 0- bit) 11 11 1111 1111 (12 - bit) n ot applicable yes offset binary code shown 0011 ? full - scale short 00 0000 0000 (1 0- bit) 0000 0000 0000 (1 2 - bit) n ot applicable yes offset binary code shown 0100 checkerboard 10 1010 1010 (1 0- bit) 1010 1010 1010 (1 2 - bit) 01 0101 0101 (1 0- bit) 0101 0101 0101 (1 2 - bit) no 0101 pn sequence long 1 n ot applicable n ot applicable yes pn23 , itu 0.150 x 23 + x 18 + 1 0110 pn sequence short 1 n ot applicable n ot applicable yes pn9 itu 0.150 x 9 + x 5 + 1 0111 one - /zero - word toggle 11 1111 1111 (1 0- bit) 1111 1111 1111 (1 2 - bit) 00 0000 0000 (1 0- bit) 0000 0000 0000 (1 2 - bit) no 1000 user input register 0x19 to register 0x1a register 0x1b to register 0x1c no 1001 1-/0 - bit toggle 10 1010 1010 (1 0- bit) 1010 1010 1010 (1 2 - bit) n ot applicable no 1010 1 sync 00 0011 1111 (1 0- bit) 0000 01 11 1111 (12 - bit) n ot applicable no 1011 one bit high 10 0000 0000 (1 0 - bit) 1000 0000 0000 (12 - bit) n ot applicable no pattern associated with the external pin 1100 mixed frequency 10 0011 0011 (1 0- bit) 1000 0110 01 11 (12 - bit) n ot applicable no 1 all test mode options except pn sequence short and pn sequence long can support 1 0 - bit to 1 2 - bit word lengths to verify data capture to the receiver. there are 12 digital output test pattern options available that can be initiated through the spi. this is a useful feature when validating receiver capture and timing. refer to table 10 for the output bit sequencing options available. some test patterns have two serial sequential words and can be alternated in various ways, depending on the test pattern chosen. note that so me patterns do not adhere to the data format select option. in addition, custom user - defined test patterns can be assigned in the 0x19, 0x1a, 0x1b, and 0x1c register addresses. the pn sequence short pattern produces a pseudorandom bit sequence that repeat s itself every 2 9 ? 1 or 511 bits. a description of the pn sequence and how it is generated can be found in section 5.1 of the itu - t 0.150 (05/96) standard. the seed value is all 1s (see table 11 for the initial values). the output is a parallel representation of the serial pn9 sequence in msb - first format. the first output word is the first 1 2 bits of the pn9 sequence in msb aligned form. table 11 . pn sequence sequence initial value next three output samples (msb first), twos complement pn sequence short 0x 7f8 0xbdf, 0x973, 0xa09 pn sequence long 0x7ff 0x7fe, 0x800, 0xfc0 the pn sequence long pattern produces a pseudorandom bit sequence that repeats itself every 2 23 ? 1 or 8,388,607 bits. a description of the pn sequence and how it is generated can be found in section 5.6 of the itu - t 0.150 (05/96) standard. the seed value is all 1s (see table 11 for the initial values) and the ad963 5 inverts the bit stream with relation to the itu standard. the output is a parallel representation of the serial pn23 sequence in msb - first format. the first output word is the first 1 2 bits of the pn23 sequence in msb aligned form . consult the memory map section for information on how to change these additional digital output timing features through the spi.
ad9635 data sheet rev. b | page 26 of 36 sdio/ pdwn pin for applications that do not require spi mod e operation, the csb pin is tied to dr vdd, and the sdio/ pdwn pin controls power - down mode according to tabl e 12. table 12. power - down mode pin settings pdwn pin voltage device mode a gnd ( d efault) r un device, normal operation dr vdd power down device note that in non - spi mode ( csb tied to dr vdd), the power - up sequence described in the power and ground g uidelines section must be adher ed to. violating the power - up sequence necessitate s a soft reset via the spi, which is not possible in non - spi mode. sclk/dfs pin the sclk/dfs pin is use d for output format selection in applications that do not require spi mode operation. this pin determines the digital output format when the csb pin is he ld high during device power - up. when sclk/dfs is tied to dr vdd, the adc output format is two s c omplement ; w hen sclk/dfs is tied to a gnd , the adc output format is o ffs et b inary . table 13 . digital output format d fs voltage output format agnd offset b inary dr vdd twos c omplement csb pin the csb pin should be tied to dr vdd for applications that do not require spi mode operation. by tying csb high, all sclk and sdio information is ignored. note that , in non - spi mode ( csb tied to dr vdd), the power - up sequence described in the power and ground g uidelines section must be adhered to . violating the power - up sequence necessitate s a soft reset via spi, which is not possible in non - spi mode. rbias pin to set the internal core bias current of the adc, place a 10.0 k ?, 1% tolerance resistor to ground at the rbias pin. output test modes the output test options are described in table 10 and are controlled by the output test mode bits at address 0x0d. when an output test mode is enabled, the analog section of the adc is disconnected from the digital back - end blocks and the test pattern is run through the output formatting block. some of the test patterns are subject to output formatting, and some are not. the pn generators from the pn sequence tests can be reset by setting bit 4 or bit 5 o f register 0x0d. these tests can be performed with or without an analog signal (if present, the analog signal is ignored), but they do require an encode clock. for more information, see the an - 877 application note , interfacing to high speed adcs via spi .
data sheet ad9635 rev. b | page 27 of 36 serial port interfac e (spi) the ad963 5 serial port interface (spi) allows the user to configure the converter for specific functions or operations through a structured register space provided inside the adc. the spi offers the user added flexibility and customization, depending on the applica tion. addresses are accessed via the serial port and can be written to or read from via the port. memory is organized into bytes that can be further divided into fields, w hich are docu - mented in the memory map section. for general o perational information, see the an - 877 application note , interfacing to high speed adcs via spi . configuratio n using the spi three pins define the spi of this adc: the sclk /dfs pin, the sdio /pdwn pin, and the csb pin (see tabl e 14 ). sclk /dfs (a serial clock when csb is low ) is used to synchronize the read and write data presented from and to the adc. sdio /pdwn (serial data input/output when csb is low ) is a dual - purpos e pin that allows data to be sent to and read from the internal adc memory map registers. csb ( chip select bar ) is an active low control that enables or disables the spi read and write cycles . table 14 . serial port interface pins pi n function sclk /dfs serial c lock when csb is low . the serial shift clock input, which is used to synchronize serial interface reads and writes. sdio /pdwn serial d ata i nput/ o utput when csb is low . a dual - purpose pin that typically serves as an input or an output, depending on the instruction being sent and the relative position in the timing frame. csb chip s elect b ar. an active low control that enables the spi mode read and write cycles. the falling edge of csb, in conjunction with the risin g edge of sclk /dfs , determines the start of the framing. an example of the serial timing is shown in figure 68. see table 5 for definitions of the timing parameters. other modes involving the csb pin are available. csb can be held low indefinitely, which permanently enables th e device ; this is called streaming. csb can stall high between bytes to allow for additional external timing. when the csb pin is tied high, spi functions are placed in high impedance mode. this mode turns on the secondary functions of the spi pin s. durin g the instruction phase of a spi operation , a 16 - bit instruction is transmitted. data follows the instruction phase, and its length is determined by the w0 and w1 bits. in addition to word length, the instruction phase determines whether the serial frame is a read or write operation, allowing the serial port to be used both to program the chip and to read the contents of the on - chip memory. the first bit of the first byte in a multibyte serial data transfer frame indicates whether a read command or a write command is issued. if the instruction is a readback operation, performing a readback causes the serial data input/ output (sdio) pin to ch ange direction from an input to an output at the appropriate point in the serial frame. all data is composed of 8 - bit words. data can be sent in msb - first mode or in lsb - first mode. msb - first mode is the default on power - up and can be changed via the spi port configuration register. for more information about this and other features, see the an - 877 application note , interfacing to high speed adcs via spi . figure 68 . serial port interface timing diagram don?t care don?t care don?t care don?t care sdio sclk csb t s t dh t clk t ds t h r/w w1 w0 a12 a11 a10 a9 a8 a7 d5 d4 d3 d2 d1 d0 t low t high 10577-062
ad9635 data sheet rev. b | page 28 of 36 hardware interface the pins described in table 14 comprise the physical interface between the user programming device and the serial port of the ad963 5 . the sclk /dfs pin and the csb pin function as inputs when using the spi interface. the sdio /pdwn pin is bidirec - tional, functioning as an input during write phases an d as an output during readback. the spi interface is flexible enough to be controlled by either fpgas or microcontrollers. one method for spi configuration is described in detail in the an - 812 application note , micro - controller - based serial port interface (spi) boot circuit . the spi port should not be active during periods when the full dynamic performance of the converter is required. because the sclk /dfs signal, the csb signal, and the sdio /pdwn signal are typically asynchrono us to the adc clock, noise from these signals can degrade converter performance. if the on - board spi bus is used for other devices, it may be necessary to provide buffers between this bus and the ad963 5 to pr event these signals from transi tioning at the converter inputs during critical sampling periods. the sclk /dfs and sdio /pdwn pins serve a dual function when the spi interface is not being used. when the pins are strapped to drvdd or ground during device power - on, they are associated with a specific function. table 12 and table 13 describe the strappable functions supported on the ad963 5 . configuration withou t the spi in applications that do not interface to the spi control registers, the sclk/dfs pin and the sdio/ pdwn pin serve as standalone cmos - compatible control pins. when the device is powered up, it is assumed that the user intends to use the pins as static control l ines for the output data format and power - down feature control. in this mode, csb should be connected to dr vdd, which disa bles the serial port interface. note that in non - sp i mode ( csb tied to dr vdd), the power - up sequence described in the power and ground g uidelines section must be adhered to . violating the power - up sequence necessitate s a soft reset via the spi, which is not possible in non - spi mode. spi accessible featu res table 15 provides a brief description of the general features that are a ccessible via the spi. these features are described in general in the an - 877 application note , interfacing to high speed adcs via spi . the ad963 5 part - specific fea tures are described in detail i n table 16 , the external memory map register table , and the following text . table 15 . features accessible using the spi feature name description power mode allows the user to set either power - down mode or standby mode clock allows the user to access the dcs, set the clock divider, and set the clock divider phase offset allows the user to digitally adjust the converter offset test i/o allows the user to set test modes to have known data on output bits output mode allows the user to set the output mode output phase allows the user to set the output clock polarity adc resolution allows for power consumption scal ing with respect to sample rate
data sheet ad9635 rev. b | page 29 of 36 memory map reading the memory m ap register table each row in the memory map register table (see table 16) has eight bit locations . the memory map is roughly divided into three sections: the chip configuration registers (address 0x00 to address 0x02); the device index and transfer registers (addr ess 0x05 and address 0xff) ; and the global adc function registers, including setup, control, and tes t (address 0x08 to address 0x10 2 ) . the memory map register table lists the default hexadecimal value for each hexadecimal address shown. the column with the heading bit 7 (msb) is the start of the default hexadecimal value given. for example, address 0x05, the device i ndex register, has a hexadecimal default value of 0x3 3 . this means that in addres s 0x05 , bit s [7: 6] = 0 0, bits [5 :4 ] = 1 1, bits[3:2] = 00, and bits[ 1 :0] = 1 1 (in binary). this setting is the default channel index setting. the default value results in both adc channels receiving the next write command. for more information on this functio n and others, see the an - 877 application note , interfacing to high speed adcs via spi. this a pplication note details the functions controlled by register 0x00 to register 0xff. the remaining registers are documented in the memory map register descriptions section. open locations all address and bit locations that are not included i n table 16 are not currently supported for this device. unused bits of a valid address location should be written with 0s. writing to these locations is r equired only when part of an address location is open (for example, address 0x05). if the entire address location is open or not listed in table 16 (for example, add ress 0x13 ) , this address location should not be written. default values after the ad963 5 is reset, critical registers are loaded with default values. the default values for the registers are given in the memory map register table, table 16. logic levels an explanation of logic level terminology follows: ? bit is set is synonymous with bit is set to logic 1 or writing logic 1 for the bit. ? clear a bit is synonymous with bit is set to logic 0 or writing logic 0 for the bit. channel - specific regis ters some channel setup functions can be programmed differently for each channel. in these cases, c hannel address locations are internally duplicated for each channel. these registers and bits are designated in table 16 as local. these local registers and bits can be accessed by setting the appropriate data channel bits (a or b) and the clock channel dco bit (bit 5) and fco bit (bit 4) in register 0x05. if all the bit s are set, the subsequent write affects the registers o f both channels and the dco/fco clock channels. in a read cycle, only one channel ( a or b ) should be set to read one of the t wo registers. if all the bits are set during a spi read cycle, the part returns the value for channel a. registers and bits that are designated as global in table 16 affect the entire part or the channel features for which independ ent settings are not allowed between channels. the settings in register 0x05 do not affect the global registers and bits.
ad9635 data sheet rev. b | page 30 of 36 m emory m ap r egister t able the ad963 5 uses a 3 - wire interface and 16 - bit addressing and , therefore , bit 0 and bit 7 in register 0x00 are set to 0, and bit 3 and bit 4 are set to 1 . when bit 5 in register 0x00 is set high, the spi enter s a soft reset , where all of the user registers revert to their default values and bit 2 is automatically cleared. table 16. addr. (hex) parameter name bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) def ault value (hex) comments chip configuration registers 0x00 spi port c onfiguration 0 = sdo active lsb f irst soft r eset 1 = 16 - bit address 1 = 16 - bit address soft r eset lsb f irst 0 = sdo active 0x18 n ibbles are mirrored to allow a given register value to perform the same function for eit her msb - first or lsb - first mode . 0x01 chip id (global) 8 - b it c hip id , bits[ 7:0 ] ad963 5 0x8 d = dual , 12- bit , 80 msps /125 msps , s er ial lvds 0x8 d unique chip id used to differentiate devices; read only. 0x02 chip grade (global) open speed grade id , bits [6:4] 100 = 80 msps 110 = 125 msps open open open open unique speed grade id used to differentiate graded devices ; r ead only. device index and transfer registers 0x05 device index open open clock c hannel dco clock c hannel fco open open data channel b data channel a 0x33 bits are set to determine which device on chip receives the next write command. d efault is all devices on chip. 0xff transfer open open open open open open open initiate o verride 0x00 set r esolution/ s ample r ate o verride . global adc function registers 0x08 power modes (global) open open open open open open power mode 00 = chip run 01 = full power - down 10 = standby 11 = reset 0x00 determines various generic modes of chip operation. 0x09 clock (global) open open open open open open open duty cycle stabilize r 0 = off 1 = on 0x00 turns duty cycle stabilizer on or off. 0x0b clock d ivide (global) open open open open open clock divide ratio [2:0] 000 = divide by 1 001 = divide by 2 010 = divide by 3 011 = divide by 4 100 = divide by 5 101 = divide by 6 110 = divide by 7 111 = divide by 8 0x00 0x0c enhancement control open open open open open chop mode 0 = off 1 = on open open 0x00 enables/ disables chop mode.
data sheet ad9635 rev. b | page 31 of 36 addr. (hex) parameter name bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) def ault value (hex) comments 0x0d test m ode (local except for pn sequence resets) user i nput t est m ode 00 = single 01 = alternate 10 = single once 11 = alternate once ( a ffects user input test mode only , bits[3:0] = 1000 ) reset pn l ong g en reset pn s hort g en output test mode , bits[3:0] (local) 0000 = off (default) 0001 = midscale short 0010 = positive fs 0011 = negative fs 0100 = alternating checkerboard 0101 = pn23 sequence 0110 = pn 9 sequence 0111 = one - /zero - word toggle 1000 = user input 1001 = 1 - /0 - bit toggle 1010 = 1 sync 1011 = one bit high 1100 = mixed bit frequency 0x00 when set, the test data is placed on the output pins in place of normal data . 0x10 offset a djust (local) 8 - bit device offset adjustment , bits [7:0] (local) offset adjust in lsbs from +127 to ?128 ( two s complement format) 0x00 device offset trim . 0x14 output mode open lvds - ansi/ lvds - ieee option 0 = lvds - ansi 1 = lvds - ieee reduced range link (global) see table 17 open open open output invert (local) open output format 0 = offset binary 1 = two s comple - ment (global) 0x01 configures the outputs and format of the data. 0x15 output adjust open open output driver termination , bits [1:0] 00 = none 01 = 200 10 = 100 11 = 100 open open open output drive 0 = 1 drive 1 = 2 drive 0x00 determines lvds or other output properties. 0x16 output phase open input clock phase adjust , bits [6:4] (value is number of input clock cycles of phase delay) ; see table 18 output clock phase adjust , bits [3:0] (0000 through 1011) ; see table 19 0x03 on devices using global clock divide, determines which phase of the divider output is used to supply the output clock. internal latching is unaffected. 0x18 v ref open open open open open internal v ref adjustment digital scheme , bits [2:0] 000 = 1.0 v p - p 001 = 1.14 v p - p 010 = 1.33 v p - p 011 = 1.6 v p - p 100 = 2.0 v p - p 0x04 select s and/or adjusts v ref . 0x19 user_patt1_lsb (global) b7 b6 b5 b4 b3 b2 b1 b0 0x00 user defined pattern 1 lsb. 0x1a user_patt1_msb (global) b15 b14 b13 b12 b11 b10 b9 b8 0x00 user defined pattern 1 msb. 0x1b user_patt2_lsb (global) b7 b6 b5 b4 b3 b2 b1 b0 0x00 user defined pattern 2 lsb. 0x1c user_patt2_ms b (global) b15 b14 b13 b12 b11 b10 b9 b8 0x00 user defined pattern 2 msb.
ad9635 data sheet rev. b | page 32 of 36 addr. (hex) parameter name bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) def ault value (hex) comments 0x21 serial output data control (global) lvds output 0 = m sb first (default) 1 = lsb first sdr/ddr one - lane/ two - lane, bit wise/ byte wise , bits [6:4] 000 = sdr two - lane, bit wise 001 = sdr two - lane, bytewise 010 = ddr two - lane, bit wise 011 = ddr two - lane, bytewise (default) 100 = ddr one - lane , wordwise encode mode 0 = normal encode rate mode (default) 1 = l ow e ncode mode for sample rate of <20 msps 0 = 1 frame (default) 1 = 2 frame serial output number of bits 10 = 12 bits (default) 11 = 10 bits 0x32 serial stream control. sample rate of < 20 msps requires that bits[6:4] = 100 (ddr one - lane) and bit 3 = 1 (low encode mode) . 0x22 serial channel s tatus (local) open open open open open open channel output reset channel power - down 0x00 used to powe r down individual sections of a converter. 0x100 resolution/ s ample rate override open resolution/ sample rate override enable resolution 10 = 12 bits 11 = 10 bits open sample rate 000 = 20 msps 001 = 40 msps 010 = 50 msps 011 = 65 msps 100 = 80 msps 101 = 105 msps 110 = 125 msps 0x00 resolution/ sample rate override (requires writing to the transfer register , 0xff). 0x101 user i/o control 2 open open open open open open open sdio pull - down 0x 00 disables sdio pull - down. 0x102 user i/o control 3 open open open open vcm power - down open open open 0x00 vcm control.
data sheet ad9635 rev. b | page 33 of 36 memory map register descriptions for additional information about functions controlled in register 0x00 to register 0xff, see the an - 877 application note , interfacing to high speed adcs via spi . device index (register 0x05) there are certain features in the map that can be set inde pen - dently for each channel, whereas other features apply globally to all channels (depending on context) , regardless of which is selected. bits[1:0] in register 0x05 can be used to select which individual data channel is affected. the output clock channels ca n be selected in register 0x05 , as well. a smaller subset of the independent feature list can be applied to those devices. transfer (register 0xff) all registers except register 0x100 are updated the moment they are written. setting bit 0 of register 0xff high initializes the settings in the adc sample rate override register (address 0x100). power modes (register 0x08) bits 2 open bits10 power mode in normal operation (bits[1:0] = 00), both adc channels are active. in power - down mode (bits[1:0] = 01) , the digital datapath clocks are disabled while the digital datapath is reset. outputs are disabled. in standby mode (bits[1:0] = 10), the digital datapath clocks and the outputs are disabled. during a digital reset (bits[1:0] = 11), all the digital datapath clocks and the outputs (where applicable) on the chip are reset , except the spi port. note that the spi is always left under control of the user; that is, it is never automatically disabled or in reset (except by power - on reset). enhancement contr ol (register 0x0c) bits3 open bit 2 chop mode for applications that are sensitive to offset voltages and other low frequency noise, such as homodyne or direct conversion receivers, chopping in the first stage of the ad963 5 is a feature that can be enabled by setting bit 2. in the frequency domain, chopping translates offsets and other low frequency noise to f clk /2 , where it can be filtered. bits[1:0] open output mode (register 0x14) bit open bit 6 lvds - ansi/lvds - ieee option setting this bit select s the lvds - ieee (reduced range) option. the default setting is lvds - ansi. w hen lvds - ansi or the lvds - ieee reduced range link is selected, the user can select the driver t ermination (see tabl e 17) . the driver current is automatically selected t o give the proper output swing. table 17 . lvds - ansi/lvds- ieee options output mode, bit 6 output mode output driver termination output driver current 0 lvds - ansi user selectable automatically selected to give proper swing 1 lvds - ieee reduced range link user selectable automatically selected to give proper swing bits[5:3] open bit 2 output invert setting this bit inverts the output bit stream. bit 1 open bit 0 output format by default, this bit is set to send the data output in two s complement format. clear ing this bit to 0 changes the output mode to offset binary. output adjust (register 0x15) bits6 open bits54 output driver term i n ati on these bits allow the user to select the internal termination resistor. bits[3:1] open bit 0 output drive bit 0 of the output adjust register controls the drive strength on the lvds driver of the fco and dco outputs only. the default va lues set the drive to 1, or the drive can be increased to 2 by setting the appropriate channel bit in register 0x05 and then setting bit 0. these features cannot be used with the output driver termina tion select. the termination selection takes precedence over the 2 driver strength on fco and dco when both the output driver termination and output drive are selected. output phase (register 0x16) bit open bits64 input c lock phase adjust when the clock divider (register 0x0b) is used, the applied clock is at a higher frequency than the internal sampling clock. bits[6:4] determine at which phase of the external clock sampling occurs. this is only applicable when the clock divider is used. s etting bits[6:4] greater than register 0x0b, bits[2:0] is prohibited. table 18 . input clock phase adjust options input clock phase adjust , bits [6:4] number of input clock cycles of phase delay 000 (default) 0 001 1 010 2 011 3 100 4 101 5 110 6 111 7
ad9635 data sheet rev. b | page 34 of 36 bits[3:0] output clock phase adjust see table 19 for details. table 19 . output clock phase adjust options output clock (dco), phase adjust , bits [3:0] dco phase adjustment (degrees relative to d0 x /d1 x edge) 0000 0 0001 60 0010 120 0011 (default) 180 0100 240 0101 300 0110 360 0111 420 1000 480 1001 540 1010 600 1011 660 serial output data control (register 0x21) the serial output data control register is used to program the ad963 5 in various output data modes , depending on the data capture solution. table 20 describes the various serialization options available in the ad963 5 . resolution/ sample rate ov erride (register 0x100) this register allow s the user to downgrade the resolution and/or the maximum sample rate (for lower power) in applications that do not require full resolution and/or sample rate . settings in this register are not initialized until bit 0 of the transfer register (register 0xff) is written high. bits[2:0] do not affect the sample rate; they affect the maximum sample rate capability of the adc. user i/o control 2 (register 0x101) bits[ 7 :1] open bit 0 sdio pull - down bit 0 can be set to disable the internal 30 k pul l- down on the sdio pin, which can be used to limit the loading when many devices are connected to the spi bus. user i/o control 3 (register 0x102) bits[7:4] open bit 3 vcm power - down bit 3 can be set high to power down t he internal vcm generator. this feature is used when applying an input common mode voltage from an external source . bits[2:0] open table 20. spi register options serialization options selected register 0x21 contents serial output number of bits (sonb) frame mode serial data mode dco multiplier timing diagram 0x3 2 12- bit 1 ddr two -l ane b yte wise 3 f s see figure 2 (default setting) 0x2 2 12- bit 1 ddr two -l ane b it wise 3 f s see figure 2 0x1 2 12- bit 1 sdr two - lane bytewise 6 f s see figure 2 0x0 2 12- bit 1 sdr two - lane bitwise 6 f s see figure 2 0x3 6 12 - bit 2 ddr two - lane bytewise 3 f s see figure 4 0x2 6 12- bit 2 ddr two - lane bitwise 3 f s see figure 4 0x1 6 12- bit 2 sdr two - lane bytewise 6 f s see figure 4 0x0 6 12- bit 2 sdr two - lane bitwise 6 f s see figure 4 0x4 2 12- bit 1 ddr one -l ane wordwise 6 f s see figure 6 0x3 3 10- bit 1 ddr two -la ne bytewise 2.5 f s see figure 3 0x2 3 10 - bit 1 ddr two - l ane bitwise 2.5 f s see figure 3 0x1 3 10- bit 1 sdr two - lane bytewise 5 f s see figure 3 0x0 3 10- bit 1 sdr two - lane bitwise 5 f s see figure 3 0x3 7 10- bit 2 ddr two - lane bytewise 2.5 f s see figure 5 0x2 7 10- bit 2 ddr two - lane bitwise 2.5 f s see figure 5 0x1 7 10- bit 2 sdr two - lane bytewise 5 f s see figure 5 0x0 7 10- bit 2 sdr two - lane bitwise 5 f s see figure 5 0x4 3 10- bit 1 ddr one -l ane wordwise 5 f s see figure 7
data sheet ad9635 rev. b | page 35 of 36 a pplications information design guidelines before starting design and layout of the ad963 5 as a system, it is recommended that the designer become familiar with these guidelines, which describe the special circuit connections and layout requirements that are needed for certain pins. power and ground g uidelines when connecting power to the ad9 635 , it is recommended that two separate 1.8 v supplies be used. use one supply for analog ( avdd); use a separate supply for the digital outputs (drvdd). for both avdd and drvdd , se veral different decoupling capa citors should be used to cover both high and low frequencies. place these capacitors close to the point of entry at the pcb level and close to the pins of the part, with minimal trace length. if two supplies are used, avdd must not power up before drvdd. drvdd must power up before, or simultaneously with, avdd. if this sequence is violated, a soft reset via spi r egister 0x00 (bits[7:0] = 0x 3c) , follo wed by a digital reset via spi r egister 0x08 (bits[7:0] = 0x 03, then bits[7:0] = 0x 00) , restore s the part to proper operation. in non - spi mode, the supply sequence is mandatory ; in this case , viola ting the supply sequence is non recoverable. a single pcb ground plane should be sufficient when using the ad963 5 . with proper decoupling and smart partitioning of the pcb analog, digital, and clock sections, optimum performance is easily achieved. clock stability cons iderations when powered on, the ad963 5 enters an initialization phase during which an internal state machine sets up the biases and the registers for proper operation. during the initia lization process, the ad963 5 needs a stable clock. if the adc clock source is not present or not stable during adc power - up, it disrupts the state mach ine and causes the adc to start up in an unknown state. to correct this, reinvoke an initialization sequence after the adc clock is stable b y issuing a digital reset via register 0x08. in the default configuration (internal v ref , ac - coupled input) where v ref and v cm are supplied by the adc itself, a stable clock during power - up is sufficient. in the case where v cm is supplied by an external source, th is , too, must be stable at power - up; otherwise, a subsequent digital reset via register 0x08 is needed. the pseudo code sequence for a digital reset is as follows: spi_write (0x08, 0x03); # digital reset spi_write (0x08, 0x00); # normal operation exposed pad thermal heat slug recommendations it is required that the exposed pad on the underside of the adc b e connected to analog ground (agnd) to achieve the best electrical and th ermal performance of the ad963 5 . an exposed continuous copper plane on the pcb should mate to the ad963 5 exposed pad, pin 0. the copper plane should have several vias to achieve the lowest possible resistive thermal path for heat dissipation to flow through the bottom of the pcb. these vias should be solder - filled or plugged. to maximize the coverage and adhesion between the adc and pcb, partition the continuous copper plane by overlaying a silkscreen on the pcb into several unifo rm sections. this provides several tie points between the adc and pcb during the reflow process, whereas using one continuous plane with no partitions only guarantees one tie point. see figure 69 for a pcb layout example. for detailed information on packaging and the pcb layout of chip scale packages, see the an - 772 application note , a design and manufact uring guide for the lead frame chip scale package (lfcsp) , at www.analog.com . figure 69 . typical pcb layout vcm the vcm pin should be decoupled to ground with a 0.1 f capacitor. reference decoupling the vref pin should be extern ally decoupled to ground with a low esr, 1.0 f capacitor in parallel with a low esr, 0.1 f ceramic capacitor. spi port the spi port should not be active during periods when the full dynamic performance of the converter is required. because the sclk, csb, and sdio signals are typically asynchronous to the adc clock, noise from these signals can degrade converter performance . if the on - board spi bus is used for other devices, it may be necessary to provide buffers between this bus and the ad963 5 to prevent these signals fr om transitioning at the converter inputs during critical sampling periods. silkscreen p artition pin 1 indic a t or 10577-063
ad9635 data sheet rev. b | page 36 of 36 outline dimensions figure 70 . 32- lead lead fram e chip scale package [lfcsp_wq] 5 mm 5 mm body, very very thin quad (cp - 32 - 12) dimensions shown in millimeters ordering guide model 1 temperature range package description package option ad9635 bcpz - 80 ? 40c to +85c 32 - l ead lead frame chip scale package (lfcsp_wq) cp - 32 - 12 ad9635 bcpzrl7 -80 ? 40c to +85c 32-l ead lead frame chip scale package (lfcsp_wq) cp -32-12 ad9635 bcpz -125 ? 40c to +85c 32-l ead lead frame chip scale package (lfcsp_wq) cp -32-12 ad9635 bcpzrl7 -125 ? 40c to +85c 32-l ead lead frame chip scale package (lfcsp_wq) cp -32-12 ad963 5 - 125ebz evaluation board 1 z = rohs compliant part. 08-16-2010-b 1 0.50 bsc bot t om view top view pin 1 indic a t or 32 9 16 17 24 25 8 exposed pa d pin 1 indic a t or sea ting plane 0.05 max 0.02 nom 0.20 ref coplanarity 0.08 0.30 0.25 0.18 5.10 5.00 sq 4.90 0.80 0.75 0.70 for proper connection of the exposed pad, refer to the pin configuration and function descriptions section of this data sheet. 0.50 0.40 0.30 0.25 min * 3.75 3.60 sq 3.55 * compliant to jedec standards mo-220- whhd-5 with the exception of the exposed pad dimension. ? 2012 C 2015 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d10577 - 0 - 10/15(b)

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